The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1.

The Spartan-3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment.

The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Table 1: Summary of Spartan-3E FPGA Attributes

DeviceSystem GatesEquivalent Logic CellsCLB Array (One CLB = Four Slices)Distributed RAM bits(1)Block RAM bits(1)Dedicated MultipliersDCMsMaximum User I/O

Maximum Differential

I/O Pairs

RowsColumnsTotal CLBsTotal SlicesXC3S100E100K2,160221624096015K72K4210840XC3S250E250K5,50834266122,44838K216K12417268XC3S500E500K10,47646341,1644,65673K360K20423292XC3S1200E1200K19,51260462,1688,672136K504K288304124XC3S1600E1600K33,19276583,68814,752231K648K368376156 SelectIO™ signaling

- Up to 633 I/O pins

- Eighteen single-ended signal standards

- Eight differential signal standards including LVDS

and RSDS

- Double Data Rate (DDR) support

• Logic resources

- Abundant logic cells with shift register capability

- Wide multiplexers

- Fast look-ahead carry logic

- Dedicated 18 x 18 multipliers

- JTAG logic compatible with IEEE 1149.1/1532

• SelectRAM™ hierarchical memory

- Up to 1,728 Kbits of total block RAM

- Up to 432 Kbits of total distributed RAM

• Digital Clock Manager (four DCMs)

- Clock skew elimination

- Frequency synthesis

- High-resolution phase shifting