The Spartan family of PROMs provides an easy-to-use, cost-effective method for storing Spartan device configuration bitstreams.

When the Spartan device is in Master Serial mode, it generates a configuration clock that drives the Spartan FPGA PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the Spartan device DIN pin. The Spartan device generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When a Spartan device is in Slave Serial mode, the PROM and the Spartan device must both be clocked by an incoming signal.

For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the Spartan device design file into a standard HEX format which is then transferred to most commercial PROM programmers.

Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan®, and Spartan-XL FPGAs

Simple interface to the Spartan device requires only one user I/O pin

Programmable reset polarity (active High or active Low)

Low-power CMOS floating-gate process

Available in 5V and 3.3V versions

Available in compact plastic 8-pin DIP, 8-pin VOIC, or 20-pin SOIC packages

Programming support by leading programmer manufacturers

Lead-free (RoHS-compliant) packaging available

Design support using the Xilinx® Alliance and Foundation™ series software packages

Guaranteed 20 year life data retention