Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to 3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support. See XCN07010 for details regarding this discontinuation, including device replacement recomendations for the XC9536XV CPLD.36 macrocells with 800 usable gates

Available in small footprint package

44-pin VQFP (34 user I/O pins)

Optimized for high-performance 2.5V systems

Low power operation

Multi-voltage operation

Advanced system features

In-system programmable

Superior pin-locking and routability with Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with individual product-term allocation

Local clock inversion with three global and one product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin inputs

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

20 year data retention

ESD protection exceeding 2,000V

Pin-compatible with 3.3V-core XC9536XL device in the 44-pin VQFP package